Videos
Building an Accelerator Functional Unit for the Intel® FPGA Programmable Acceleration Card N3000
Intel
In this training you will learn about building an accelerator functional unit (AFU) for the Intel® FPGA programmable acceleration card (PAC) N3000. The methodology described will use a hardware description language to define your AFU and integrate it with the required IPs. You will utilize the provided reference AFU design and supported Core Cache Interface (CCI-P), PCI-e, Ethernet & NIC interfaces to seamlessly build your design into an FPGA loadable image using Intel Quartus® Prime software. This training also provides an overview of the Intel FPGA PAC N3000 card and CCI-P interface. You will also learn how an FPGA image can be uploaded into an actual Intel FPGA PAC N3000 card.
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