Videos
Integrating Memory Interfaces IP in Intel® FPGA Devices
Intel
This training is part 2 of 4. Intel® Stratix® 10, Arria® 10, and Cyclone® 10 devices introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 2.666 Gbps on some devices. This part of the training discusses how to use the IP Parameter Editor in the Intel Quartus® Prime Pro edition software or Platform Designer to create and parameterize the altera_emif IP for a standard FPGA or an SoC variant. It also shows how to constrain the IP in a device using either the Pin Planner or Interface Planner, found only in the Intel Quartus Prime Pro Edition software. Finally, resource sharing is presented to demonstrate how easy it is to implement multiple interfaces in a single device with minimal resource usage.
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