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视频中心

Converting a Zynq*-7000 / Zynq UltraScale+* MPSoC Design to Agilex™ 5

Altera
In this course, I go over hardware differences of the Zynq UltraScale+* AMD* FPGA with the Altera® Agilex™ 5 device.  I will go over converting primitives and intellectual property (IP) including the memory interfaces on the FPGA fabric along with the memory interfaces for the embedded systems.  I talk about the differences in the I/O as well as the clocking between the two devices.  I spend time on the differences between the embedded portions of the FPGAs and go over the flows for building the embedded software.

References:
https://www.intel.com/content/www/us/...
https://www.intel.com/content/www/us/...
https://www.intel.com/content/www/us/...
https://www.intel.com/content/www/us/...
https://www.intel.com/content/www/us/...
https://github.com/altera-opensource/...
https://github.com/altera-opensource/...
https://www.rocketboards.org/foswiki/...
https://www.intel.com/content/www/us/...
https://www.intel.com/content/www/us/...
https://www.rocketboards.org/foswiki/...
https://www.intel.com/content/www/us/...
https://cdrdv2-public.intel.com/71528...
https://www.intel.com/content/www/us/...
https://www.intel.com/content/www/us/...
https://www.intel.com/content/www/us/...
https://www.intel.com/content/www/us/...
https://www.intel.com/content/www/us/...
https://www.intel.com/content/www/us/...
https://www.intel.com/content/www/us/...
https://www.intel.com/content/www/us/...
https://www.intel.com/content/www/us/...

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