NXP LPC4300 series-First asymmetrical, dual-core digital signal controller 2012/07/25 NXP Semiconductors
Processor/Memory
A dual-core architecture and a unique set of confi gurable peripherals make it possible to develop DSP and MCU applications within a single architecture and development environment.
Key features ・204 MHz, 32-bit ARM Cortex-M4 ・204 MHz, 32-bit ARM Cortex-M0 coprocessor ・Up to 1 MB dual-bank Flash ・Up to 264 KB SRAM ・Up to 4 KB EEPROM ・Memory Protection Unit (MPU) ・Two high-speed USB 2.0 interfaces, with on-chip high-speed PHY ・10/100T Ethernet MAC with MII and RMII interfaces ・LCD controller with 1024 x 768 pixel display resolution ・Innovative Quad SPI Flash Interface (SPIFI) ・State Confi gurable Timer (SCT) Subsystem ・Confi gurable Serial GPIO ・Two CAN 2.0B ・AES Decryption with 128-bit secure OTP key storage ・Up to 164 GPIO ・Pin-compatible with the LPC1800 series
Additional features ・8-channel GPDMA controller ・Two 8-channel, 400 Ksps 10-bit ADCs and one 10-bit DAC ・Motor Control PWM and Quadrature Encoder Interface ・Four UARTs, smart card interface ・Two Fast-mode I2C, two I2S, three SSP/SPI ・Temperature range: –40 to +85 ºC
High Performance and Lower Power Combined with large accelerated Flash and SRAM memories and a set of unique confi gurable peripherals, the 204 MHz LPC4300 enables customers to develop a wide range of applications such as motor control, power management,industrial automation, robotics, medical, automotiveaccessories and embedded audio.
Combining MCU and DSP capabilities The Cortex-M4 processor combines the benefi ts of a microcontroller – integrated interrupt control, low power modes, low cost debug and ease of use – with highperformance digital signal processing features such as single-cycle MAC, single instruction multiple data (SIMD) techniques, saturating arithmetic, and a fl oating point unit.A Cortex-M0 coprocessor offl oads many of the data movement and I/O handling duties that can drain the bandwidth of the Cortex-M4 core. This allows the Cortex-M4 to concentrate fully on crunching numbers for digital signal control applications.
Extensive peripheral set The LPC4300 features three new innovative peripherals: a flexible SPI Flash Interface, a State Configurable Timer subsystem and Serial GPIO. The State Configurable Timer Subsystem consists of a timer array with a state machine enabling complex functionality, including event-controlled PWM waveform generation, ADC synchronization, and dead-time control. The SPI Flash Interface provides a seamless high-speed memory-mapped connection to virtually all SPI and quad-SPI manufacturers. The LPC4300’s Serial GPIO, available for the first time, allows a developer the flexibility to interface to any non-standard serial interface or to mimic multiple standard serial interfaces (such as I2S, TDM for multichannel audio, I2C and more).
Additional peripherals available on the LPC4300 include two HS USB controllers, an on-chip HS PHY, a 10/100T Ethernet controller with hardware enabled TCP/IP checksum calculation,a high-resolution color LCD controller, and AES decryption,including two 128-bit secure OTP memories for key storage.Versions with AES encryption are available on request.
Companies Website:
http://components-asiapac.arrow.com/en/new_product/4763/
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